PXN20PB Datasheet, PDF (16/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking

Features
• Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
• DMA transfers possible between system memories, SPIs, I²C, ADC, UART, eMIOS200 and
General Purpose I/Os
• Programmable DMA channel mux allows assignment of any DMA source to any available DMA
channel with up to a total of 64 potential request sources.
2.6.17 Crossbar Switch (XBAR)
The Crossbar Switch allows concurrent accesses between masters and slaves, and provides these features:
• Up to 6 master ports
— Masters: Z6 CPU, Z0 CPU, eDMA, FlexRay, FEC, MLB
• Multiple bus slaves to enable access to flash, SRAM ports and peripherals
• Multiple AIPS bridges to support connection to all peripheral modules
• Crossbar supports consecutive transfers from master to available slaves
• 32-bit internal address bus, 32-bit internal data bus
• User configurable priority arbitration based for masters
• Temporary dynamic priority elevation for IOP and DMA
2.6.18 Memory Protection Unit (MPU)
The MPU provides the following features:
• Supports up to 16 region descriptors for per-master protection
• Start and end address defined with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for 4 concurrent read ports
• Read and write attributes for all masters
• Execute and supervisor/user mode attributes for processor masters
2.6.19 Interrupt Controller (INTC)
The PXN20 implements an interrupt controller that features the following:
• Unique 9-bit vector for each of the 316 separate interrupt sources (22 reserved)
• 8 software triggerable interrupt sources
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the priority ceiling protocol for accessing
shared resources.
• External high priority interrupt directly accessing the main core critical interrupt mechanism
PXN20 Product Brief, Rev. 1
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Freescale Semiconductor