K10P104M100SF2 Datasheet, PDF (49/60 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DS15
DS13
First data
DS14
DS12
Data
DS11
Last data
DS16
DSPI_SIN
First data
Data
Last data
Figure 20. DSPI Classic SPI Timing — Slave Mode
ry _{6.8.3 SDHC Specifications}
a _{The following timing specs are defined at the chip I/O pin and must be translated}
in ^{appropriately to arrive at timing specs/constraints for the physical interface.}
Num
SD1
SD2
SD3
SD4
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
Table 38. SDHC switching specifications
Description
Card input clock
lim ^{Clock frequency (low speed)}
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
e Clock frequency (identification mode)
Min.
0
0
0
0
r ^{Clock low time}
7
Clock high time
7
P^{Clock rise time}
—
Max.
400
25
20
400
—
—
3
Unit
kHz
MHz
MHz
kHz
ns
ns
ns
SD5
t_THL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
t_OD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
t_THL
SDHC input setup time
5
—
ns
SD8
t_THL
SDHC input hold time
0
—
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
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