MCIMX27_08 Datasheet, PDF (48/132 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Table 18. WR0 Sequence Timing Parameters
ID
OW5
OW6
Parameter
Write 0 Low Time
Transmission Time Slot
Symbol
t_{WR0_low}
t_SLOT
Min
60
OW5
Typical
Max
Units
100
120
µs
117
120
µs
Figure 6 depicts Write 1 Sequence timing, Figure 7 depicts the Read Sequence timing, and Table 19 lists
the timing parameters.
One-Wire bus
(BATT_LINE)
OW8
One-Wire bus
(BATT_LINE)
OW7
Figure 6. Write 1 Sequence Timing Diagram
OW8
OW7
OW9
Figure 7. Read Sequence Timing Diagram
ID
OW7
OW8
OW9
Table 19. Write 1/Read Timing Parameters
Parameter
Write 1/Read Low Time
Transmission Time Slot
Release Time
Symbol
Min
Typical
t_LOW1
1
5
t_SLOT
60
117
t_RELEASE
15
Max
15
120
45
Units
µs
µs
µs
3.5.3 ATA Electrical Specifications
This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6
specification.
NOTE
The parallel ATA module is not available on the i.MX27L
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
48
Freescale Semiconductor
Preliminary—Subject to Change Without Notice