MCIMX27_08 Datasheet, PDF (16/132 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Functional Description and Application Information
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
• Independent DMA engine with multiple channels allowing transmit data, transmit descriptor,
receive data, and receive descriptor accesses to provide high performance
• Independent RISC-based controller that provides the following functions in the FEC:
— Initialization (those internal registers not initialized by the user or hardware)
— High level control of the DMA channels (initiating DMA transfers)
— Interpreting buffer descriptors
— Address recognition for receive frames
— Random number generation for transmit collision backoff timer
• The Message Information Block (MIB) in FEC maintains counters for a variety of network events
and statistics. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters.
2.3.14 General Purpose I/O Module (GPIO)
The general-purpose input/output (GPIO) module provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When it is configured as an output, you can write to an internal
register to control the state driven on the output pin. When configured as an input, you can detect the state
of the input by reading the state of an internal register. The GPIO includes all of the general purpose
input/output logic necessary to drive a specific data to the pad and control the direction of the pad using
registers in the GPIO module. The ARM926 is able to sample the status of the corresponding pads by
reading the appropriate status register. The GPIO supports up to 32 interrupts and has the ability to identify
interrupt edges as well as generate three active high interrupts.
2.3.15 General Purpose Timer (GPT)
The i.MX27/MX27L processors contains six identical 32-bit General Purpose Timers (GPT) with
programmable prescalers and compare and capture registers. Each timer’s counter value can be captured
using an external event, and can be configured to trigger a capture event on the rising or/and falling edges
of an input pulse. Each GPT can also generate an event on the TOUT pin, and an interrupt when the timer
reaches a programmed value. Each GPT has an 11-bit prescaler that provides a programmable clock
frequency derived from multiple clock sources, including ipg_clk_32k, ipg_clk_perclk, ipg_clk_perclk/4,
and external clock from the TIN pin. The counter has two operation modes: free-run and restart mode. The
GPT can work in low-power mode.
2.3.16 Inter IC Communication (I²C)
Inter IC Communication (I²C) is a two-wire, bidirectional serial bus that provides a simple, efficient
method of data exchange, minimizing the interconnection between devices. This bus is suitable for
applications requiring occasional communications over a short distance between many devices. The
flexible I²C enables additional devices to be connected to the bus for expansion and system development.
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
16
Freescale Semiconductor
Preliminary—Subject to Change Without Notice