MCF5271EC Datasheet, PDF (47/56 Pages) Freescale Semiconductor, Inc – 32-bit Embedded Controller Division

Preliminary Electrical Characteristics
Table 36. I²C Output Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num
Characteristic
Min
Max
Units
I7 ¹ Data setup time
2
—
t_cyc
I8 ¹ Start condition setup time (for repeated start
20
—
t_cyc
condition only)
I9 ¹ Stop condition setup time
10
—
t_cyc
NOTES:
1 _{Note: Output numbers depend on the value programmed into the IFDR; an IFDR}
programmed with the maximum frequency (IFDR = 0x20) results in minimum output
timings as shown in Table 36. The I²C interface is designed to scale the actual data
transition time to move it to the middle of the I2C_SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the
numbers given in Table 36 are minimum values.
2 _{Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can}
only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on
external signal capacitance and pull-up resistor values.
3 _{Specified at a nominal 50-pF load.}
Figure 14 shows timing for the values in Table 35 and Table 36.
I2C_SCL
I1
I2
I4
I6
I7
I5
I8
I3
I9
I2C_SDA
Figure 14. I²C Input/Output Timings
8.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
8.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and
ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.
Table 37 lists MII receive channel timings.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
47