MCF5271EC Datasheet, PDF (43/56 Pages) Freescale Semiconductor, Inc – 32-bit Embedded Controller Division

Preliminary Electrical Characteristics
Figure 10 shows an SDRAM read cycle.
SD_CKE
D1
A[23:0]
D2
RAS
CAS ¹
0123
D3
Row
D4
D2
SDWE
D[31:0]
D2
RAS[1:0]
CAS[3:0]
D2
ACTV
NOP
1 _{DACR[CASL] = 2}
4567
D4
READ
NOP
8 9 10 11 12 13 14 15
Column
D4
D2
D6
D5
NOP
D4
PALL
Figure 10. SDRAM Read Cycle
Table 32. SDRAM Timing
NUM
Characteristic
D1 CLKOUT high to SDRAM address valid
D2 CLKOUT high to SDRAM control valid
D3 CLKOUT high to SDRAM address invalid
D4 CLKOUT high to SDRAM control invalid
D5 SDRAM data valid to CLKOUT high
D6 CLKOUT high to SDRAM data invalid
D7¹ CLKOUT high to SDRAM data valid
D8² CLKOUT high to SDRAM data invalid
NOTES:
1 _{D7 and D8 are for write cycles only.}
Symbol
Min
t_CHDAV
—
t_CHDCV
—
t_CHDAI
1.5
t_CHDCI
1.5
t_DDVCH
4
t_CHDDI
1.5
t_CHDDVW
—
t_CHDDIW
1.5
Max Unit
9
ns
9
ns
—
ns
—
ns
—
ns
—
ns
9
ns
—
ns
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Freescale Semiconductor
43