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K30P121M100SF2 Datasheet, PDF (46/61 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Peripheral operating requirements and behaviors
6.8.1 CAN switching specifications
See General switching specifications.
6.8.2 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master mode DSPI timing (low-speed mode)
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
1.71
—
4 x tBCLK
(tSCK/2) - 4
(tSCK/2) - 4
(tSCK/2) - 4
—
-2
15
0
Max.
3.6
12.5
—
(tSCK/2) + 4
—
—
10
—
—
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
46
DS3
DS2
DS1
DS4
DS7
DS8
First data
DS5
First data
Data
Last data
DS6
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.