IMX28CEC Datasheet, PDF (46/70 Pages) Freescale Semiconductor, Inc – Processors Data Sheet for Consumer Products

3.5.9 Inter IC (I²C) Timing
The I²C module is designed to support up to 400-Kbps I²C connection compliant with I²C bus protocol.
The following section describes I²C SDA and SCL signal timings.
Figure 25 shows the timing of the I²C module. Table 50 describes the I²C module timing parameters
(IC1–IC11) shown in the figure.
I2C_SDA
IC10
IC11
IC9
IC2
I2C_SCL
IC8
IC4
IC7
IC3
START
IC10
IC11
START
IC6
IC5
IC1
Figure 25. I²C Module Timing Diagram
STOP
START
Table 50. I²C Module Timing Parameters: 1.8 V – 3.6 V
Standard Mode
Fast Mode
ID
Parameter
Unit
Min. Max.
Min.
Max.
IC1 I2C_SCL cycle time
10
—
2.5
—
μs
IC2 Hold time (repeated) START condition
4.0
—
0.6
—
μs
IC3 Set-up time for STOP condition
IC4 Data hold time
4.0
—
0.6
0¹
3.45²
0¹
—
μs
0.9²
μs
IC5 HIGH Period of I2C_SCL clock
4.0
—
0.6
—
μs
IC6 LOW Period of the I2C_SCL clock
4.7
—
1.3
—
μs
IC7 Set-up time for a repeated START condition
IC8 Data set-up time
4.7
—
250
—
0.6
100³
—
μs
—
ns
IC9 Bus free time between a STOP and START condition
4.7
—
1.3
—
μs
IC10
IC11
Rise time of both I2C_SDA and I2C_SCL signals
Fall time of both I2C_SDA and I2C_SCL signals
—
1000 20+0.1C_b4 300
ns
—
300 20+0.1C_b4 300
ns
IC12 Capacitive load for each bus line (C_b)
—
400
—
400
pF
1 _{A device must internally provide a hold time of at least 300 ns for the I2C_SDA signal in order to bridge the undefined region}
of the falling edge of I2C_SCL.
2 _{The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal.}
3 _{A fast-mode I2C bus device can be used in a standard-mode I}2_{C bus system, but the requirement of Set-up time (ID No IC7)}
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal.
If such a device does stretch the LOW period of the I2C_SCL signal, it must output the next data bit to the I2C_SDA line
max_rise_time (ID No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus
specification) before the I2C_SCL line is released.
4 _{Cb = total capacitance of one bus line in pF.}
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
46
Freescale Semiconductor