MCIMX31_09 Datasheet, PDF (45/118 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors

SDCLK
SDCLK
CS
SD4
RAS
SD4
SD5
CAS
SD5
SD4
SD4
WE
SD5
SD5
SD6
ADDR
ROW/BA
SD7
COL/BA
SD10
DQ
SD1
SD2
SD3
SD8
SD9
Data
Electrical Characteristics
SD4
DQM
Note: CKE is high during the read/write cycle.
SD5
Figure 33. SDRAM Read Cycle Timing Diagram
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD1
SDRAM clock high-level width
SD2
SDRAM clock low-level width
SD3
SDRAM clock cycle time
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
SD6
Address setup time
SD7
Address hold time
SD8
SDRAM access time
Symbol
Min
Max
Unit
tCH
tCL
tCK
tCMS
tCMH
tAS
tAH
tAC
3.4
4.1
ns
3.4
4.1
ns
7.5
—
ns
2.0
—
ns
1.8
—
ns
2.0
—
ns
1.8
—
ns
—
6.47
ns
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
45