56F805 Datasheet, PDF (44/56 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

MSCAN_RX
CAN receive
data pin
(Input)
T _WAKEUP
Figure 3-28 Bus Wakeup Detection
3.14 JTAG Timing
Table 3-18 JTAG Timing^{1, 3}
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50pF, f_OP = 80MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation²
f_OP
DC
10
MHz
TCK cycle time
t_CY
100
—
ns
TCK clock pulse width
t_PW
50
—
ns
TMS, TDI data set-up time
t_DS
0.4
—
ns
TMS, TDI data hold time
t_DH
1.2
—
ns
TCK low to TDO data valid
t_DV
—
26.6
ns
TCK low to TDO tri-state
t_TS
—
23.5
ns
TRST assertion time
t_TRST
50
—
ns
DE assertion time
t_DE
4T
—
ns
1. Timing is both wait state- and frequency-dependent. For the values listed, T = clock cycle. For 80MHz operation,
T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
V_IH
TCK
(Input)
V_M = V_IL + (V_IH – V_IL)/2
t_CY
t_PW
V_M
V_IL
t_PW
V_M
Figure 3-29 Test Clock Input Timing Diagram
56F805 Technical Data, Rev. 15
44
Freescale Semiconductor