56F805 Datasheet, PDF (13/56 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

2.5 Interrupt and Program Control Signals
Interrupt and Program Control Signals
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
1
1
1
Signal
Name
IRQA
IRQB
RESET
Signal
Type
Input
(Schmitt)
Input
(Schmitt)
Input
(Schmitt)
State
During
Reset
Input
Input
Input
Signal Description
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1
RSTO
Output Output Reset Output—This output reflects the internal reset state of the
chip.
1
EXTBOOT
Input
Input External Boot—This input is tied to V_DD to force device to boot
(Schmitt)
from off-chip memory. Otherwise, it is tied to V_SS.
56F805 Technical Data, Rev. 15
Freescale Semiconductor
13