MC56F847XX Datasheet, PDF (43/69 Pages) Freescale Semiconductor, Inc – MC56F847xx Advance

System modules
Table 25. 12-bit ADC Electrical Specifications (continued)
Characteristic
Input Capacitance
Sampling Capacitor
• 1x mode
• 2x mode
• 4x mode
Symbol
Min
Typ
Max
C_ADI
Unit
pF
1.4
2.8
5.6
1. If the ADC’s reference is from V_DDA: When V_DDA is below 3.0 V, the ADC functions but ADC specifications are not
guaranteed.
2. When the input is at the V_refl level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset
and gain error. When the input is at the V_refh level the output will be all ones (hex FFF), minus any error contribution due to
offset and gain error.
3. ADC clock duty cycle min/max is 45/55%
4. When V_refh is supplied externally
5.
6.
I_NL measured from V_IN = V_REFL to V_IN =
LSB = Least Significant Bit = 0.806 mV
aVt^R3^EF.^H3.
V
VDDA,
x1
Gain
Setting
7. Offset over the conversion range of 0025 to 4080
8. Measured converting a 1 kHz input Full Scale sine wave
9. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
8.5.1.1 Equivalent Circuit for ADC Inputs
The following figure illustrates the ADC input circuit during sample and hold. S1 and S2
are always opened/closed at non-overlapping phases and operate at the ADC clock
frequency. The following equation gives equivalent input impedance when the input is
selected.
1
(ADC ClockRate)
 x 1.4x10^-12
+
100ohm + 125ohm
C1: Single Ended Mode
2XC1: Differential Mode
Analog Input
Channel Mux
125 ESD
equivalent resistance
Resistor
100Ohms
S1
1
2
3
S1
S2
(V_REFHx - V_REFLx ) / 2
C1
C1
S2
S1
S/H
S1
C1: Single Ended Mode
2XC1: Differential Mode
MC56F847xx Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
Preliminary
43
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