MC56F847XX Datasheet, PDF (28/69 Pages) Freescale Semiconductor, Inc – MC56F847xx Advance

General
Table 7. DC Electrical Characteristics at Recommended Operating Conditions (continued)
Characteristic
Oscillator Input Current
Low
DAC Output Voltage
Range
Output Current¹
High Impedance State
Schmitt Trigger Input
Hysteresis
Symbol
Notes¹
Min
Typ
I_ILOSC
Pin Group 3
—
0
V_DAC
Pin Group 5 Typically
—
V_SSA +
40mV
I_OZ
Pin Groups
—
0
1, 2
V_HYS
Pin Groups 0.06 x V_DD
—
1, 2
Max
+/- 2
Typically
V_DDA -
40mV
+/- 1
—
Unit
µA
V
µA
Test
Conditions
V_IN = 0V
R_LD = 3 kΩ ||
C_LD = 400 pf
—
V
—
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET, GPIOA7
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC
7.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 8. Reset, Stop, Wait, and Interrupt Timing
Characteristic
Minimum RESET Assertion Duration
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first instruction
(exiting Stop)
Symbol
t_RA
t_RDA
t_IF
Typical
Min
16¹
TBD
361.3
Typical
Max
—
16²
570.9
Unit
ns
ns
ns
1. If Reset pin filter is enabled, minimum pulse assertion must be greater than 21 ns
2. This value is true if the user sets to 1 the RST_FLT bit in the SIM_CTRL register.
NOTE
In the formulae, T = system clock cycle and T_osc = oscillator
clock cycle. For an operating frequency of 100 MHz, T = 10 ns.
At 4 MHz (used coming out of reset and stop modes),
T = 250 ns.
See
Figure
—
—
—
MC56F847xx Advance Information Data Sheet, Rev. 2, 06/2012.
28
Preliminary
Freescale Semiconductor, Inc.
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