XPC8240LZU200E Datasheet, PDF (4/8 Pages) Freescale Semiconductor, Inc – MPC8240 Part Number Specification for the XPC8240RXXnnnx Series

PLL Configurations
Freescale Semiconductor, Inc.
Table 5. Preliminary Power Consumption (continued)
Mode
33/66/233
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Unit Notes
33/83/250 33/100/200 33/100/250 66/100/200 66/100/250
Typical—GV_DD
300
900
mW 7, 9
Notes:
1. The values include V_DD, AV_DD, AV_DD2, and LAV_DD but do not include I/O supply power; see Section 1.7.2, “Power
Supply Sizing,” in the MPC8240 Integrated Processor Hardware Specifications for information on OV_DD and GV_DD
supply power. One DIMM is used for memory loading.
2. Maximum—FP power is measured at V_DD = 2.625 V with dynamic power management enabled while running an
entirely cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at V_DD = 2.625 V with dynamic power management enabled while running
entirely cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at V_DD = 2.625 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at V_DD = AV_DD = 2.625 V, OV_DD = 3.3 V where a nominal FP value, a nominal INT value,
and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries
to local memory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the MPC8240 performing cache resident integer operations
at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8. The typical maximum OV_DD value resulted from the MPC8240 operating at the fastest frequency combination of
66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and
zeros to PCI memory.
9. The typical maximum GV_DD value resulted from the MPC8240 operating at the fastest frequency combination of
66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and
zeros on 64-bit boundaries to local memory.
1.5 PLL Configurations
The MPC8240 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)
frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the
MPC8240 is shown in Table 18.
Table 18. MPC8240 Microprocessor PLL Configurations
250-MHz Part ^{8, 9}
Ratios ^{3, 4}
Ref.
No.
PLL_
CFG
[0:4] ²
CPU ¹
HID1[0:4]
PCI Clock Input
(PCI_SYNC_IN)
Range (MHz)
Peripheral
Logic/Mem
Bus Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI to Mem
(Mem VCO)
Multiplier
Mem to CPU
(CPU VCO)
Multiplier
0 00000 00110
1 00001 11000
2 00010 00101
3 00011 00101
4 00100 00101
25–33
25–27
50–56 ⁵
25–28 ⁵
75–100
75–83
50–56
Bypass
50–56
188–250
225–250
100–112
100–113
3 (6)
3 (6)
1 (4)
Bypass
2 (8)
2.5 (5)
3 (6)
2 (8)
2 (8)
2 (8)
4
MPC8240 Part Number Specification for the XPC8240RXXnnnx Series
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