MC34652 Datasheet, PDF (4/25 Pages) Freescale Semiconductor, Inc – 2.0 A Negative Voltage Hot Swap Controller with Enhanced Programmability

MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
Power MOSFET Energy Capability
Continuous Output Current ⁽²⁾
Maximum Voltage
DISABLE Terminal
UV Terminal
OV, ILIM, ICHG, and TIMER Terminals
PG Terminal (V_PG - V_IN)
PG Terminal (V_PG - V_IN)
All Terminals Minimum Voltage
PG, PG Maximum Current
ESD Voltage, All Terminals
Human Body Model ⁽³⁾
Machine Model ⁽⁴⁾
V_PWR
85
V
E_MOSFET
Varies ⁽¹⁾
mJ
I_{O (CONT)}
2.0
A
V
—
V_IN - 0.3 to V_PWR + 5.5
—
7.0
—
5.0
—
85
—
85
—
- 0.3
V
—
Internally Limited
A
V
V_ESD3
± 2000
V_ESD4
± 200
THERMAL RATINGS
Storage Temperature
Operating Temperature
Ambient ⁽⁵⁾
Junction
Peak Package Reflow Temperature During Solder Mounting ⁽⁶⁾
Thermal Resistance ^{(7), (8)}
Junction-to-Ambient, Single-Layer Board ⁽⁹⁾
Junction-to-Ambient, Four-Layer Board ⁽¹⁰⁾
T_STG
T_A
T_J
T_SOLDER
R_θJA
R_θJMA
-65 to 150
-40 to 85
-40 to 160
260
103
65
°C
°C
°C
°C/W
Notes
1. Refer to the section titled Power MOSFET Energy Capability on page 22 for a detailed explanation on this parameter.
2. Continuous output current capability so long as T_J is ≤ 160°C.
3. ESD1 testing is performed in accordance with the Human Body Model (C_ZAP=100pF, R_ZAP=1500 Ω).
4. ESD2 testing is performed in accordance with the Machine Model (C_ZAP=200 pF, R_ZAP=0 Ω).
5. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
7. Refer to the section titled Thermal Shutdown on page 15 for more thermal resistance values under various conditions.
8. The VOUT and VIN terminals comprise the main heat conduction paths.
9. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
10. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the
board.
34652
4
Analog Integrated Circuit Device Data
Freescale Semiconductor