33932 Datasheet, PDF (4/21 Pages) Freescale Semiconductor, Inc – 5.0 A Throttle Control H-Bridge

PIN CONNECTIONS
Table 1. 33932 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Description section beginning on page 11.
Pin
Pin
Pin Name _Function
Formal Name
Definition
14-16
17,18,26-28
19
OUT4
VPWRB
CCPB
Power
Output
H-Bridge Output 4
Power Input Positive Power
Supply
Analog
Output
Charge Pump
Capacitor
H-bridge B Source of high side MOSFET2 and drain of low side MOSFET2.
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
External reservoir capacitor connection for H-bridge B internal charge pump;
connected to VPWRB. Allowable values are 30 to 100 nF. Note: This capacitor
is required for the proper performance of the device.
20
IN4
Logic Input
Input 4
Logic input control of OUT4.
21
IN3
Logic Input
Input 3
Logic input control of OUT3.
22
SFB
Logic
Status Flag B H-bridge B open drain active LOW Status Flag output (requires an external pull-
Output -
(Active Low)
up resistor to V_DD. Maximum permissible load current < 0.5 mA. Maximum
Open Drain
V_CEsat < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
23
D3
Logic Input Disable Input 3 When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated. Schmitt trigger
(Active High)
input with ~80 μA source so default condition = disabled.
24
FBB
Analog
Feedback B
H-bridge B load current feedback output provides ground referenced 0.24% of
Output
the high side output current. (Tie to GND through a resistor if not used.)
25
29-31
36-38
41
EN/D4
OUT3
OUT2
CCPA
Logic Input
Power
Output
Power
Output
Analog
Output
Enable Input
H-Bridge Output 3
H-Bridge Output 2
Charge Pump
Capacitor
When EN/D4 is logic HIGH, H-bridge B is operational. When EN/D4 is logic
LOW, the H-bridge B outputs are tri-stated and H-bridge B is placed in Sleep
Mode. (logic input with ~ 80μA sink so default condition = Sleep Mode.)
H-bridge B Source of high side MOSFET1 and drain of low side MOSFET1.
H-Bridge A source of high side MOSFET2 and drain of low side MOSFET2.
External reservoir capacitor connection for H-bridge A internal charge pump;
connected to VPWRA. Allowable values are 30 to 100 nF. Note: This capacitor
is required for the proper performance of the device.
42
IN2
Logic Input
Input 2
Logic input control of OUT2.
43
IN1
Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to
VPWRA, and when IN1 is logic LOW, OUT1 is set to PGNDA. (Schmitt trigger
Input with ~ 80 μA source so default condition = OUT1 HIGH.)
44
SFA
Logic
Status Flag
H-Bridge A open drain active LOW Status Flag output (requires an external
Output -
Open Drain
(Active Low)
pull-up resistor to V_DD. Maximum permissible load current < 0.5 mA. Maximum
V_CEsat < 0.4 V @ 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
TAB
AGNDA
Analog
Analog Signal ^{The low-current analog signal ground must be connected to PGND via low-}
AGNDB Ground
Ground
impedance path (<<10 mΩ, 0 Hz to 20 kHz). Exposed TAB is also the main
heatsinking path for the device.
33932
4
Analog Integrated Circuit Device Data
Freescale Semiconductor