MC68HC05SR3 Datasheet, PDF (39/96 Pages) Freescale Semiconductor, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units

UNSTACKING
ORDER
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
•
•
•
51
CONDITION CODE REGISTER
42
ACCUMULATOR
33
24
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
5
15
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 5-1 Interrupt Stacking Order
Register
—
—
—
—
TCR
—
Table 5-1 Reset/Interrupt Vector Addresses
Flag Name
—
—
—
—
TIF
—
Interrupt
Reset
Software
External Interrupt
External Interrupt 2
Timer Overflow
Keyboard
CPU Interrupt
RESET
SWI
IRQ
IRQ2
TIF
KBI
Vector Address
$1FFE-$1FFF
$1FFC-$1FFD
$1FFA-$1FFB
$1FF8-$1FF9
$1FF6-$1FF7
$1FF4-$1FF5
Priority
highest
lowest
5.2.1 Non-maskable Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by
the contents of memory locations $1FFC and $1FFD.
MC68HC05SR3
RESETS AND INTERRUPTS
TPG
Freescale
5-3