MC34708 Datasheet, PDF (38/159 Pages) Freescale Semiconductor, Inc – Power Management Integrated Circuit (PMIC) for i.MX50/53 Families

Functional Block Description
of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the
PUMSx pins in the respective time slot defined in the sequencer selection.
RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts
running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is
generated, and RESETB will go high.
7.5.2.11 Internal MemHold Power Cut
As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power
Cut state if PCUTs are enabled. The backup coin cell will now supply the MC34708 core, along with the 32 k crystal oscillator,
the RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as
possible.
Both RESETB and RESETBMCU are tripped, bringing the entire system down, along with the supplies and external clock drivers,
so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.
If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply
recovery.
7.5.3 Power Control Logic
7.5.3.1 Power Cut Description
When the supply at VALWAYS drops below the UVDET threshold, due to battery bounce or battery removal, the Internal
MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the
RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled.
The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the
PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed
value, and therefore does not have to be reprogrammed after each power cut.
If power is not re-established above the LOWBATT threshold before the PCUT timer expires, the state machine transitions to the
Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an
“unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down.
Upon re-application of power before expiration (a “successful PCUT”, defined as VALWAYS first rising above the UVDET
threshold and then battery above the LOWBATT threshold before the PCUT timer expires), a Cold Start is engaged after the
UVTIMER has expired.
In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by
software. The PCI interrupt is cleared by software or when cycling through the Off state.
Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance
of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current
through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power
down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize
the chance of a product falling into and getting stuck in ambulance mode.
First, the successful recovery out of a PCUT requires the VABTT node to rise above LOBATT threshold, providing hysteretic
margin from the LOBATTT (H to L) threshold. Secondly, the number of times the PCUT mode is entered is counted with the
counter PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through SPI. When the contents of both
become equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires.
After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor
reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the
PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not
enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a
PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1
(See Silent Restart from PCUT Event).
Analog Integrated Circuit Device Data
Freescale Semiconductor
MC34708
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