10XS3435_09 Datasheet, PDF (38/51 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Dual 10 mOhm, Dual 35 mOhm)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Bit D0 (OC_mode_sel) allows to select the over-current
mode, as described Table 19.
Table 19. Over-current Mode Selection
OC_mode_s (D0)
Over-current Mode
0
only inrush current management (default)
1
inrush current and bulb cooling
management
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
The GCR register allows the MCU to configure the device
through the SPI.
Bit D8 allows the MCU to enable or disable the VDD failure
detector. A logic [1] on VDD_FAIL_en bit allows switch of the
outputs HS[0:3] with PWMR register device in Fail-safe mode
in case of V_DD < V_DD(FAIL).
Bit D7 allows the MCU to enable or disable the PWM
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as
reference by PWM module, as described in the following
Table 20.
Table 20. PWM Module Selection
PWM_en (D7) CLOCK_sel (D6)
PWM module
0
X
PWM module disabled
(default)
1
0
PWM module enabled with
external clock from IN0
1
1
PWM module enabled with
internal calibrated clock
Bits D5:D4 allow the MCU to select one of two analog
feedback on CSNS output pin, as shown in Table 21.
Table 21. CSNS Reporting Selection
TEMP_en CSNS_en
(D5)
(D4)
CSNS reporting
0
0
CSNS tri-stated (default)
X
1 current recopy of selected output (D3:2] bits)
1
0
temperature on GND flag
10XS3435
38
Table 22. Output Current Recopy Selection
CSNS1 (D3) CSNS0 (D2)
CSNS reporting
0
0
HS0 (default)
0
1
HS1
1
0
HS2
1
1
HS3
The GCR register disables the over-voltage protection
(D0). When this bits is [0], the over-voltage is enabled (default
value).
ADDRESS 00111 — CALIBRATION REGISTER
(CALR)
The CALR register allows the MCU to calibrate internal
clock, as explained in Figure 13.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-)
first as the new message data is clocked into the SI pin. The
first sixteen bits of data clocking out of the SO, and following
a CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the CS pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, PWMR, CONFR0, CONFR1
and OCR registers.
Note that the SO data will continue to reflect the
information for each output (depending on the previous
SOA4, SOA3 state) that was selected during the most recent
STATR write until changed with an updated STATR write.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the CS is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exception:
Analog Integrated Circuit Device Data
Freescale Semiconductor