10XS3435_09 Datasheet, PDF (34/51 Pages) Freescale Semiconductor, Inc – Quad High Side Switch (Dual 10 mOhm, Dual 35 mOhm)

FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
Open-load Detection In On State
The ON output open-load current thresholds can be
chosen by SPI to detect a standard bulbs or LEDs
(OLLED[0:3] bit set to logic [1]). In the case where load
current drops below the defined current threshold OLON bit
is set to logic [1], the output stays ON and FS is not disturbed.
Open-load Detection In On State For Led
Open load for LEDs only (OLLED[0:3] set to logic [1]) is
detected periodically each t _OLLED (fully-on, D[6:0]=7F). To
detect OLLED in fully-on state, the output must be ON at least
t _OLLED.
To delatch the diagnosis, the condition should be removed
and SPI read operation is needed (OL_ON[0:3] bit). The ON
output open-load protection can be disabled through SPI
(OLON_DIS[0:3] bit).
Analog Current Recopy and Temperature Feedbacks
The CSNS pin is an analog output reporting a current
proportional to the designed output current or a voltage
proportional to the temperature of the GND flag (pin #14).
The routing is SPI programmable (TEMP_en, CSNS_en,
CSNS_s[1,0] and CSNS_ratio_s bits).
In case the current recopy is active, the CSNS output
delivers current only during ON time of the output switch
without overshoot. The maximum current is 2.0 mA typical.
The typical value of external CSNS resistor connected to the
ground is 2.5 kΩ.
The current recopy is not active in Fail-safe mode.
Temperature Prewarning Detection
In Normal mode, the 10XS3435 provides a temperature
prewarning reported via SPI in case of the temperature of the
GND flag is higher than T_OTWAR. This diagnosis (OTW bit set
to [1]) is latched in the SPI DIAGR0 register. To delatch, a
read SPI command is needed.
ACTIVE CLAMP ON VPWR
The device provides an active gate clamp circuit in order
to limit the maximum transient VPWR voltage at
VPWR_(CLAMP). In case of overload on an output the
corresponding output is turned off which leads to high voltage
at VPWR with an inductive VPWR line. When VPWR voltage
exceeds VPWR_(CLAMP) threshold, the turn-off on the
corresponding output is deactivated and all HS[0:3] outputs
are switched ON automatically to demagnetize the inductive
Battery line.
For a long battery line between the battery and the device
(> 20 meters), the smart high side switch output may exceed
the energy capability in case of a short-circuit. It is
recommended to implement a voltage transient suppressor
to drain the battery line energy.
REVERSE BATTERY ON VPWR
The output survives the application of reverse voltage as
low as -18 V. Under these conditions, the ON resistance of
the output is 2 times higher than typical ohmic value in
forward mode. No additional passive components are
required except on VDD current path.
GROUND DISCONNECT PROTECTION
In the event the 10XS3435 ground is disconnected from
load ground, the device protects itself and safely turns OFF
the output regardless of the state of the output at the time of
disconnection (maximum V_PWR = 16 V). A 10 kΩ resistor
needs to be added between the MCU and each digital input
pin in order to ensure that the device turns off in case of
ground disconnect and to prevent this pin from exceeding
maximum ratings.
LOSS OF SUPPLY LINES
Loss of VDD
If the external VDD supply is disconnected (or not within
specification: VDD < VDD_(FAIL)) with VDD_FAIL_en bit is set
to logic [1]), all SPI register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 3]
if V_PWR is within specified voltage range. The 10XS3435
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
Fail-safe device operation with no V_DD supplied. In this state,
the over-temperature, over-current, severe short-circuit,
short to VPWR and OFF open-load circuitry are fully
operational with default values corresponding to all SPI bits
are set to logic [0]. No current is conducted from V_PWR to
V_DD.
Loss of VPWR
If the external VPWR supply is disconnected (or not within
specification), the SPI configuration, reporting, and daisy
chain features are provided for RST to set to logic [1] under
V_DD in nominal conditions. This fault condition can be
diagnosed with UV fault in SPI STATR_s registers. The SPI
pull-up and pull-down current sources are not operational.
The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected
(or not within specification: (VDD and VPWR) <
V_SUPPLY(POR)), all SPI register contents are reset with default
values corresponding to all SPI bits are set to logic [0] and all
latched faults are also reset.
10XS3435
34
Analog Integrated Circuit Device Data
Freescale Semiconductor