MC3S12RG128_1 Datasheet, PDF (378/546 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
Module Base + 0xXXXD
R
W
Reset:
7
PRIO7
0
6
PRIO6
5
PRIO5
4
PRIO4
3
PRIO3
2
PRIO2
0
0
0
0
0
Figure 12-35. Transmit Buffer Priority Register (TBPR)
1
PRIO1
0
0
PRIO0
0
Read: Anytime when TXEx flag is set (see Section 12.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Write: Anytime when TXEx flag is set (see Section 12.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
12.3.3.5 Time Stamp Register (TSRH–TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 12.3.2.1,
“MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Module Base + 0xXXXE
R
W
Reset:
7
TSR15
x
6
TSR14
5
TSR13
4
TSR12
3
TSR11
2
TSR10
x
x
x
x
x
Figure 12-36. Time Stamp Register — High Byte (TSRH)
1
TSR9
x
0
TSR8
x
Module Base + 0xXXXF
R
W
Reset:
7
TSR7
x
6
TSR6
5
TSR5
4
TSR4
3
TSR3
2
TSR2
x
x
x
x
x
Figure 12-37. Time Stamp Register — Low Byte (TSRL)
1
TSR1
x
0
TSR0
x
MC3S12RG128 Data Sheet, Rev. 1.06
378
Freescale Semiconductor