MC3S12RG128_1 Datasheet, PDF (285/546 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.4 Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 10-6. Output Compare 7 Data Register (OC7D)
1
OC7D1
0
0
OC7D0
0
Read or write anytime.
A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer
port data register depending on the output compare 7 mask register.
10.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004–0x0005
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R _{tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt tcnt}
W ^{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-7. Timer Count Register (TCNT)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read (any mode)/
write (test mode) for high byte and low byte will give a different result than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
MC3S12RG128 Data Sheet, Rev. 1.06
Freescale Semiconductor
285