DSP56311 Datasheet, PDF (35/96 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

AC Electrical Characteristics
Table 2-9. DRAM Page Mode Timings, Three Wait States^1,2,3 (Continued)
100 MHz
No.
Characteristics
Symbol
Expression⁴
Unit
Min Max
134 CAS deassertion to data not valid (read hold time)
t_OFF
0.0
—
ns
135 Last CAS assertion to RAS deassertion
t_RSH
2.5 × T_C −4.0
21.0
—
ns
136 Previous CAS deassertion to RAS deassertion
t_RHCP
4.5 × T_C −4.0
41.0
—
ns
137 CAS assertion pulse width
138 Last CAS deassertion to RAS assertion⁵
• BRW[1–0] = 00, 01—not applicable
• BRW[1–0] = 10
• BRW[1–0] = 11
t_CAS
t_CRP
2 × T_C −4.0
—
4.75 × T_C −6.0
6.75 × T_C −6.0
16.0
—
ns
—
—
—
41.5
—
ns
61.5
—
ns
139 CAS deassertion pulse width
t_CP
1.5 × T_C −4.0
11.0
—
ns
140 Column address valid to CAS assertion
t_ASC
T_C −4.0
6.0
—
ns
141 CAS assertion to column address not valid
t_CAH
2.5 × T_C −4.0
21.0
—
ns
142 Last column address valid to RAS deassertion
t_RAL
4 × T_C −4.0
36.0
—
ns
143 WR deassertion to CAS assertion
t_RCS
1.25 × T_C −4.0
8.5
—
ns
144 CAS deassertion to WR assertion
t_RCH
0.75 × T_C −4.0
3.5
—
ns
145 CAS assertion to WR deassertion
t_WCH
2.25 × T_C −4.2
18.3
—
ns
146 WR assertion pulse width
t_WP
3.5 × T_C −4.5
30.5
—
ns
147 Last WR assertion to RAS deassertion
t_RWL
3.75 × T_C −4.3
33.2
—
ns
148 WR assertion to CAS deassertion
t_CWL
3.25 × T_C −4.3
28.2
—
ns
149 Data valid to CAS assertion (write)
t_DS
0.5 × T_C – 4.5
0.5
—
ns
150 CAS assertion to data not valid (write)
t_DH
2.5 × T_C −4.0
21.0
—
ns
151 WR assertion to CAS assertion
t_WCS
1.25 × T_C −4.3
8.2
—
ns
152 Last RD assertion to RAS deassertion
t_ROH
3.5 × T_C −4.0
31.0
—
ns
153 RD assertion to data valid
154 RD deassertion to data not valid⁶
t_GA
2.5 × T_C −5.7
—
19.3 ns
t_GZ
0.0
—
ns
155 WR assertion to data active
0.75 × T_C – 1.5
6.0
—
ns
156 WR deassertion to data high impedance
0.25 × T_C
—
2.5
ns
Notes: 1. The number of wait states for Page mode access is specified in the DRAM Control Register.
2. The refresh period is specified in the DRAM Control Register.
3. The asynchronous delays specified in the expressions are valid for the DSP56311.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t_PC equals 4 ×
T_C for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or
maximum value listed, as appropriate.
5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t_OFF and not t_GZ.
Freescale Semiconductor
DSP56311 Technical Data, Rev. 8
2-15