DSP56311 Datasheet, PDF (34/96 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

Specifications
2.4.5.2 DRAM Timing
The selection guides in Figure 2-12 and Figure 2-15 are for primary selection only. Final selection should be based
on the timing in the following tables. For example, the selection guide suggests that four wait states must be used
for 100 MHz operation with Page Mode DRAM. However, consulting the appropriate table, a designer can evaluate
whether fewer wait states might suffice by determining which timing prevents operation at 100 MHz, running the
chip at a slightly lower frequency (for example, 95 MHz), using faster DRAM (if it becomes available), and
manipulating control factors such as capacitive and resistive load to improve overall system performance.
DRAM type
(tRAC ns)
Note:
This figure should be used for primary selection. For exact
and detailed timings, see the following tables.
100
80
70
60
Chip frequency
50
40
66
80
100
120 ^(MHz)
1 Wait states
3 Wait states
2 Wait states
4 Wait states
Figure 2-12. DRAM Page Mode Wait State Selection Guide
Table 2-9. DRAM Page Mode Timings, Three Wait States^1,2,3
No.
Characteristics
Symbol
Expression⁴
131 Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
132 CAS assertion to data valid (read)
133 Column address valid to data valid (read)
t_PC
t_CAC
t_AA
4 × T_C
3.5 × T_C
2 × T_C −5.7
3 × T_C −5.7
100 MHz
Unit
Min Max
40.0
—
ns
35.0
—
ns
—
14.3 ns
—
24.3 ns
2-14
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor