|
MC9S12XDP512CAL Datasheet, PDF (336/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
|
◁ |
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
When PACN1 overï¬ows from 0x00FF to 0x0000, the interrupt ï¬ag PBOVF in PBFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
MC9S12XDP512 Data Sheet, Rev. 2.21
336
Freescale Semiconductor
|
▷ |