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MC9S12XDP512CAL Datasheet, PDF (179/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.13 ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the
result registers based on two criteria. First there is left and right justiï¬cation; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2âs complement format and only exists in left
justiï¬ed format. Signed data selected for right justiï¬ed format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
5.3.2.13.1 Left Justiï¬ed Result Data
7
R BIT 9 MSB
R BIT 7 MSB
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
BIT 5
BIT 3
0
2
BIT 4
BIT 2
0
1
BIT 3
BIT 1
0
0
BIT 2
BIT 0
0
Figure 5-15. Left Justiï¬ed, ATD Conversion Result Register, High Byte (ATDDRxH)
10-bit data
8-bit data
R
R
W
Reset
7
6
5
4
3
2
1
0
BIT 1
BIT 0
0
0
0
0
0
0
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-16. Left Justiï¬ed, ATD Conversion Result Register, Low Byte (ATDDRxL)
5.3.2.13.2 Right Justiï¬ed Result Data
R
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BIT 9 MSB BIT 8 10-bit data
0
0
0
0
0
0
0
0
8-bit data
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-17. Right Justiï¬ed, ATD Conversion Result Register, High Byte (ATDDRxH)
7
R BIT 7
R BIT 7 MSB
6
BIT 6
BIT 6
5
BIT 5
BIT 5
4
BIT 4
BIT 4
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
BIT 3
BIT 3
0
2
BIT 2
BIT 2
0
1
BIT 1
BIT 1
0
0
BIT 0
BIT 0
10-bit data
8-bit data
0
Figure 5-18. Right Justiï¬ed, ATD Conversion Result Register, Low Byte (ATDDRxL)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
179
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