56F8346_07 Datasheet, PDF (31/178 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Signal Pins
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
SCLK0
130
Schmitt
Input,
SPI 0 Serial Clock — In the master mode, this pin serves as an
Input/
pull-up output, clocking slaved listeners. In slave mode, this pin serves as
Output
enabled the data clock input.
(GPIOE4)
Schmitt
Input/
Output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
MOSI0
(GPIOE5)
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
132
Input/
In reset, SPI 0 Master Out/Slave In — This serial data pin is an output from
Output
output is a master device and an input to a slave device. The master device
disabled, places data on the MOSI line a half-cycle before the clock edge the
pull-up is slave device uses to latch the data.
enabled
Input/
Port E GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is MOSI0.
MISO0
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
131
Input/
Input,
SPI 0 Master In/Slave Out — This serial data pin is an input to a
Output
pull-up master device and an output from a slave device. The MISO line of
enabled a slave device is placed in the high-impedance state if the slave
device is not selected. The slave device places data on the MISO
line a half-cycle before the clock edge the master device uses to
latch the data.
(GPIOE6)
Input/
Output
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
31
Preliminary