56F803_07 Datasheet, PDF (31/52 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

External Bus Asynchronous Timing
Table 3-10 External Bus Asynchronous Timing^{1, 2} (Continued)
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50pF, f_op = 80MHz
Characteristic
Symbol
Min
Max
Unit
Input Data Hold to RD Deasserted
RD Assertion Width
Wait states = 0
Wait states > 0
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
Address Valid to RD Asserted
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
t_DRD
t_RD
t_AD
t_ARDA
t_RDD
t_WRRD
t_RDRD
t_WRWR
t_RDWR
0
19
(T*WS) + 19
—
—
-4.4
—
—
6.8
0
14.1
12.8
—
ns
—
ns
—
ns
1
ns
(T*WS) + 1
ns
—
ns
2.4
ns
(T*WS) + 2.4
ns
—
ns
—
ns
—
ns
—
ns
56F803 Technical Data, Rev. 16
Freescale Semiconductor
31