MCF53017_10 Datasheet, PDF (30/62 Pages) Freescale Semiconductor, Inc – Version 3 ColdFire® core with EMAC

Preliminary Electrical Characteristics
5.7.2 DDR SDRAM AC Timing Characteristics
When the SDRAM controller is configured for DDR SDRAM, the following timing numbers must be followed to properly latch
or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. The following timing numbers
are subject to change at anytime, and are only provided to aid in early board design.
Table 14. DDR Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit Notes
Frequency of Operation
DD1 Clock Period
DD2 Pulse Width High
DD3 Pulse Width Low
DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] Output Valid
t_DDCK
t_DDSK
t_DDCKH
t_DDCKL
t_SDCHACV
50
80
Mhz
1
12.5
20
ns
2
0.45
0.55
SD_CLK
3
0.45
0.55
SD_CLK
3
—
0.5 × SD_CLK ns
4
+ 1.0
DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
t_SDCHACI
2.0
SD_CS[1:0] Output Hold
—
ns
DD6 Write Command to first DQS Latching Transition
DD7 Data and Data Mask Output Setup (DQ-->DQS)
Relative to DQS (DDR Write Mode)
DD8 Data and Data Mask Output Hold (DQS-->DQ)
Relative to DQS (DDR Write Mode)
DD9 Input Data Skew Relative to DQS (Input Setup)
DD10 Input Data Hold Relative to DQS.
t_CMDVDQ
—
t_DQDMV
1.5
t_DQDMI
1.0
t_DVDQ
t_DIDQ
—
0.25 × SD_CLK
+ 0.5ns
1.25
—
—
1
—
SD_CLK
ns
5
6
ns
7
ns
8
ns
9
DD11 DQS falling edge from SDCLK rising (output hold time) t_DQLSDCH
0.5
—
ns
DD12 DQS input read preamble width
t_DQRPRE
0.9
1.1
SD_CLK
DD13 DQS input read postamble width
t_DQRPST
0.4
0.6
SD_CLK
DD14 DQS output write preamble width
t_DQWPRE
0.25
—
SD_CLK
DD15 DQS output write postamble width
t_DQWPST
0.4
0.6
SD_CLK
1 _{The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the}
same frequency as the internal bus clock.
2 _{SD_CLK is one SDRAM clock in (ns).}
3 _{Pulse width high plus pulse width low cannot exceed min and max clock period.}
4 _{Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,}
and voltage variations.
5 _{This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger}
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
SD_D[31:24] is relative to SD_DQS3, SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and
SD_D[7:0] is relative SD_DQS0.
6 _{The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats}
will be valid for each subsequent DQS edge.
7 _{This specification relates to the required hold time of today’s DDR memories. SD_D[31:24] is relative to SD_DQS3,}
SD_D[23:16] is relative to SD_DQS2, SD_D[15:8] is relative to SD_DQS1, and SD_D[7:0] is relative SD_DQS0.
MCF5301x Data Sheet, Rev. 5
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor