MC14LC5480 Datasheet, PDF (3/24 Pages) Freescale Semiconductor, Inc – 5 V PCM Codec-Filter

Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
POWER SUPPLY
VDD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 5 V. This pin should be decoupled to VSS with a
0.1 µF ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
This output pin provides a mid–supply analog ground reg-
ulated to 2.4 V. This pin should be decoupled to VSS with a
0.01 µF to 0.1 µF ceramic capacitor. All analog signal pro-
cessing within this device is referenced to this pin. If the au-
dio signals to be processed are referenced to VSS, then
special precautions must be utilized to avoid noise between
VSS and the VAG pin. Refer to the applications information in
this document for more information. The VAG pin becomes
high impedance when this device is in the powered down
mode.
CONTROL
Mu/A
Mu/A Law Select (Pin 16)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu–Law companding is selected
when this pin is connected to VDD and A–Law companding is
selected when this pin is connected to VSS.
PDI
Power–Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO+, RO–, PO–, PO+, TG, VAG, and DT to
become high impedance. The device will operate normally
when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
state, which prevents the DT PCM output from going low im-
pedance for at least two FST cycles. The filters must settle
out before the DT PCM output or the RO+ or RO– receive
analog outputs will represent a valid analog signal.
ANALOG INTERFACE
TI +
Transmit Analog Input (Non–Inverting) (Pin 19)
This is the non–inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the VSS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to VDD minus 2 V. This is an FET
gate input. Connecting the TI+ pin to VDD will place this am-
plifier’s output (TG) into a high–impedance state, thus allow-
ing the TG pin to serve as a high–impedance input to the
transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting op-
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to VDD – 2 V. This is an FET gate input.
Connecting the TI+ pin to VDD will place this amplifier’s out-
put (TG) into a high–impedance state, thus allowing the TG
pin to serve as a high–impedance input to the transmit filter.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to VDD will place this amplifier’s output (TG) into a high–
impedance state, thus allowing the TG pin to serve as a
high–impedance input to the transmit filter. All signals at this
pin are referenced to the VAG pin. This pin is high impedance
when the device is in the powered down mode.
RO+
Receive Analog Output (Non–Inverting) (Pin 1)
This is the non–inverting output of the receive smoothing
filter from the digital–to–analog converter. This output is
capable of driving a 2 kΩ load to 1.575 V peak referenced to
the VAG pin. This pin is high impedance when the device is in
the powered down mode.
RO–
Receive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 1.575 V peak referenced to the VAG
pin. This pin is high impedance when the device is in the
powered down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the
VAG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to VDD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
This is the inverting power amplifier output, which is used
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300 Ω load to PO+. The PO+ and PO– outputs are
differential (push–pull) and capable of driving a 300 Ω load to
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
and signal reference of this output is the VAG pin. The VAG
pin cannot source or sink as much current as this pin, and
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