MC14LC5480 Datasheet, PDF (17/24 Pages) Freescale Semiconductor, Inc – 5 V PCM Codec-Filter

Freescale Semiconductor, Inc.
DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE
(VDD = 5.0 V ± 5%, TA = – 40 to + 85°C, CL = 150 pF, See Figure 6 and Note 1)
Ref.
No.
Characteristics
Min
Max
Unit
42
Time Between Successive FSC Pulses
Note 2
43
DCL Clock Frequency
512
6176
kHz
44
DCL Clock Pulse Width High
50
—
ns
45
DCL Clock Pulse Width Low
50
—
ns
46
Hold Time of FSC After Falling Edge of DCL
20
—
ns
47
Setup Time of FSC to DCL Falling Edge
60
—
ns
48
Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of Dout
—
60
ns
49
Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of Dout
—
60
ns
50
Rising Edge of DCL to Valid Data on Dout
—
60
ns
51
Second DCL Falling Edge During LSB to High Impedance of Dout
10
50
ns
52
Setup Time of Din Before Rising Edge of DCL
20
—
ns
53
Hold Time of Din After DCL Rising Edge
—
60
ns
NOTES:
1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words
are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).
42
FSC
(FST)
DCL
(BCLKT)
49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
50
51
50
48
51
Dout (DT)
52
MSB CH1
CH2
CH3 ST1
ST2
ST3 LSB
MSB CH1
CH2 CH3
ST1
ST2
ST3 LSB
53
53
52
Din (DR)
MSB CH1
CH2 CH3 ST1
ST2
ST3
LSB
MSB CH1
CH2 CH3
ST1 ST2
ST3
LSB
46
FSC
(FST)
DCL
(BCLKT)
46
47
1
48
Dout (DT)
2
49
MSB
52
53
Din (DR)
MSB
43
44
3
4
5
45
CH1
CH1
Figure 6. GCI Interface Timing
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