56F801_1 Datasheet, PDF (3/48 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

56F801 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
• 8K × 16-bit words (16KB) Program Flash
• 1K × 16-bit words (2KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 1K × 16-bit words (2KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCE^TM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4
A/D2 ADC
4
VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC V_DD
2
4
V_SS
5*
V_DDA
V_SSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2
GPIO
COP/
Watchdog
Applica-
SPI
tion-Specific
4
or
GPIO
Memory &
Peripherals
••
PAB
PDB
•
XDB2
• ^CGDB
•
•
XAB1
XAB2
•
•
INTERRUPT
IPBB
CONTROLS CONTROLS
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
*includes TCS pin which is reserved for factory use and is tied to VSS
56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
56F801 Technical Data, Rev. 17
Freescale Semiconductor
3