56F801_1 Datasheet, PDF (29/48 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing^{1, 5}
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
t_RAZ
—
Signals High Impedance
21
ns Figure 3-13
Minimum RESET Assertion Duration²
OMR Bit 6 = 0
OMR Bit 6 = 1
t_RA
Figure 3-13
275,000T
—
ns
128T
—
ns
RESET De-assertion to First External Address
Output
t_RDA
33T
34T
ns Figure 3-13
Edge-sensitive Interrupt Request Width
t_IRW
1.5T
—
ns Figure 3-14
IRQA, IRQB Assertion to External Data Memory
t_IDM
15T
Access Out Valid, caused by first instruction
execution in the interrupt service routine
—
ns Figure 3-15
IRQA, IRQB Assertion to General Purpose Output
t_IG
16T
Valid, caused by first instruction execution in the
interrupt service routine
—
ns Figure 3-15
IRQA Low to First Valid Interrupt Vector Address
t_IRI
13T
Out recovery from Wait State³
—
ns Figure 3-16
IRQA Width Assertion to Recover from Stop State⁴
t_IW
2T
—
ns Figure 3-17
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t_IF
Figure 3-17
—
275,000T
ns
—
12T
ns
Duration for Level Sensitive IRQA Assertion to
t_IRQ
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-18
—
275,000T
ns
—
12T
ns
Delay from Level Sensitive IRQA Assertion to First
t_II
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
Figure 3-18
—
275,000T
ns
—
12T
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F801 Technical Data, Rev. 17
Freescale Semiconductor
29