MSC8256 Datasheet, PDF (29/68 Pages) Freescale Semiconductor, Inc – Six-Core Digital Signal Processor

Electrical Characteristics
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (V_OD) has
the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In
other words, V_OD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V_DIFFp) is 500 mV.
The peak-to-peak differential voltage (V_DIFFp-p) is 1000 mV p-p.
2.5.2.2 SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK.
Figure 5 shows a receiver reference diagram of the SerDes reference clocks.
SR[1–2]_REF_CLK
50 Ω
SR[1–2]_REF_CLK
50 Ω
Input
Amp
Figure 5. Receiver of SerDes Reference Clocks
The characteristics of the clock signals are as follows:
• The supply voltage requirements for V_DDSXC are as specified in Table 3.
• The SerDes reference clock receiver reference circuit structure is as follows:
— The SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in
Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-Ω
termination to GND_SXC followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA)
while the minimum common mode input level is 0.1 V above GND_SXC. For example, a clock with a 50/50 duty
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SR[1–2]_REF_CLK and SR[1–2]_REF_CLK inputs cannot drive 50 Ω to GND_SXC DC or
the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled
externally.
• The input amplitude requirement is described in detail in the following sections.
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
29