MSC8256 Datasheet, PDF (27/68 Pages) Freescale Semiconductor, Inc – Six-Core Digital Signal Processor

Electrical Characteristics
2.5.1.3 DDR2/DDR3 SDRAM Capacitance
Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory.
Note: At recommended operating conditions (see Table 3) with V_DDDDR = 1.8 V for DDR2 memory or V_DDDDR = 1.5 V for
DDR3 memory.
Table 8. DDR2/DDR3 SDRAM Capacitance
Parameter
Symbol
Min
Max
Unit
I/O capacitance: DQ, DQS, DQS
C_IO
6
8
pF
Delta I/O capacitance: DQ, DQS, DQS
C_DIO
—
0.5
pF
Notes: 1. This parameter is sampled. V_DDDDR = 1.8 V ± 0.1 V (for DDR2), f = 1 MHz, T_A = 25°C, V_OUT = V_DDDDR/2,
V_OUT (peak-to-peak) = 0.2 V.
2. This parameter is sampled. V_DDDDR = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T_A = 25°C, V_OUT = V_DDDDR/2,
V_OUT (peak-to-peak) = 0.175 V.
Notes
1, 2
1, 2
2.5.1.4 DDR Reference Current Draw
Table 9 lists the current draw characteristics for MV_REF.
Note: Values when used at recommended operating conditions (see Table 3).
Table 9. Current Draw Characteristics for MV_REF
Parameter / Condition
Symbol
Min
Current draw for MV_REFn
• DDR2 SDRAM
• DDR3 SDRAM
I_MVREFn
—
Max
300
250
Unit
μA
μA
2.5.2 High-Speed Serial Interface (HSSI) DC Electrical Characteristics
The MSC8256 features an HSSI that includes two 4-channel SerDes ports used for high-speed serial interface applications (PCI
Express, Serial RapidIO interfaces, and SGMII). This section and its subsections describe the common portion of the SerDes
DC, including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter (Tx) and receiver (Rx)
reference circuits. The data lane circuit specifications are specific for each supported interface, and they have individual
subsections by protocol. The selection of individual data channel functionality is done via the Reset Configuration Word High
Register (RCWHR) SerDes Protocol selection fields (S1P and S2P). Specific AC electrical characteristics are defined in
Section 2.6.2, “HSSI AC Timing Specifications.”
2.5.2.1 Signal Term Definitions
The SerDes interface uses differential signaling to transfer data across the serial link. This section defines terms used in the
description and specification of differential signals. Figure 4 shows how the signals are defined. For illustration purposes only,
one SerDes lane is used in the description. Figure 4 shows the waveform for either a transmitter output (SR[1–2]_TX and
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
27