MC56F8006 Datasheet, PDF (28/100 Pages) Freescale Semiconductor, Inc – Digital Signal Controller

Memory Maps
5 Memory Maps
5.1 Introduction
The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent
memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only
in program space.
This section provides memory maps for:
• Program address space, including the interrupt vector table
• Data address space, including the EOnCE memory and peripheral memory maps
On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use
Restrictions” column of Table 6.
Table 6. Chip Memory Configurations
On-Chip Memory
Program Flash
(PFLASH)
Unified RAM (RAM)
56F8006
8K x 16
or
16 KB
1K x 16
or
2 KB
56F8002
6K x 16
or
12 KB
1K x 16
or
2 KB
Use Restrictions
Erase/program via flash interface unit and word writes to CDBW
Usable by the program and data memory spaces
5.2 Program Map
The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory
buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be
read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read.
Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory
space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or
tables can be stored and accessed in program memory.
The program memory map is shown in Table 7 and Table 8.
Table 7. Program Memory Map¹ for 56F8006 at Reset
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
P: 0x00 83FF
P: 0x00 8000
RESERVED
On-Chip RAM²: 2 KB
P: 0x00 7FFF
P: 0x00 2000
RESERVED
P: 0x00 1FFF
P: 0x00 0000
• Internal program flash: 16 KB
• Interrupt vector table locates from 0x00 0000 to 0x00 0065
• COP reset address = 0x00 0002
• Boot location = 0x00 0000
1 _{All addresses are 16-bit word addresses.}
2 _{This RAM is shared with data space starting at address X: 0x00 0000; see Figure 7.}
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
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Freescale Semiconductor