MC56F8006 Datasheet, PDF (1/100 Pages) Freescale Semiconductor, Inc – Digital Signal Controller

Freescale Semiconductor
Preliminary Technical Data
Document Number: MC56F8006
Rev. 2, 03/2009
MC56F8006/MC56F8002
Digital Signal Controller
MC56F8006/MC56F8002
48-pin LQFP
Case: 932-03
7 x 7 mm²
28-pin SOIC
Case: 751F-05
7.5 x 18 mm²
32-pin LQFP
Case: 873A-03
7 x 7 mm²
The 56F8006/56F8002 is a member of the 56800E core-based
family of digital signal controllers (DSCs). It combines, on a
single chip, the processing power of a DSP and the
functionality of a microcontroller with a flexible set of
peripherals to create an extremely cost-effective solution.
Because of its low cost, configuration flexibility, and compact
program code, the 56F8006/56F8002 is well-suited for many
applications. The 56F8006/56F8002 includes many
peripherals that are especially useful for cost-sensitive
applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a dual Harvard-style architecture
consisting of three execution units operating in parallel,
allowing as many as six operations per instruction cycle. The
MCU-style programming model and optimized instruction set
allow straightforward generation of efficient, compact DSP
and control code. The instruction set is also highly efficient
for C compilers to enable rapid development of optimized
control applications.
The 56F8006/56F8002 supports program execution from
internal memories. Two data operands can be accessed from
the on-chip data RAM per instruction cycle. The
56F8006/56F8002 also offers up to 40 general-purpose
input/output (GPIO) lines, depending on peripheral
configuration.
The 56F8006/56F8002 digital signal controller includes up to
16 KB of program flash and 2 KB of unified data/program
RAM. Program flash memory can be independently bulk
erased or erased in small pages of 512 bytes (256 words).
On-chip features include:
• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8006: 16 KB (8K x 16) flash memory
– 56F8002: 12 KB (6K x 16) flash memory
– 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Two 28-channel, 12-bit analog-to-digital converters
(ADCs)
• Two programmable gain amplifiers (PGA) with gain up to
32x
• Three analog comparators
• One programmable interval timer (PIT)
• One high-speed serial communication interface (SCI) with
LIN slave functionality
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
• One SMBus compatible inter-integrated circuit (I²C) port
• One real time counter (RTC)
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz
(400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, and 48-pin LQFP packages
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.