EB632 Datasheet, PDF (27/112 Pages) Freescale Semiconductor, Inc – Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M)

HDI16
ICR is a read/write control register that allows the use of bit manipulation instructions on control register bits. The
host processor uses the ICR to control the HDI16 interrupts and flags. The SC140 core cannot access the ICR. The
HPCR[DMA] bit and the HCR[HICR] bit control the function of the ICR bits.
Table 23. 2K87M Mask Set ICR Bit Descriptions
Name
HRRA
0–1
HTRA
2–3
—
4
HF0
5
HF1
6
—
7
INIT
8
Description
HDI Receive Request Assertion
00
The receive request is asserted a specified time based on the number of ₀₁
data bytes to receive.
10
11
HDI Transmit Request Assertion
00
The transmit request is asserted a specified time based on the number of
data bytes to transmit.
01
10
11
Reserved. Write to zero for future compatibility.
Settings
HRRQ asserted for 8 bytes (RX full)
HRRQ asserted for 16 bytes (RX full + 1
HOTX entry full)
HRRQ asserted for 32 bytes (RX full + 3
HOTX entries full)
Reserved
HTRQ/HREQ asserted for 8 bytes (TX
empty)
HTRQ/HREQ asserted for 16 bytes (TX
empty + 1 HOTX entry empty)
HTRQ/HREQ asserted for 32 bytes (TX
empty + 3 HOTX entries empty)
Reserved
Host Flag 0
A general-purpose flag for host-to-core communication. The host
processor can set or clear HF0. HF0 is reflected in the HSR on the core
side of the HDI16.
Host Flag 1
A general-purpose flag for host-to-core communication. The host
processor can set or clear HF1. HF1 is reflected in the HSR on the core
side of the HDI16.
Reserved. Write to zero for future compatibility.
Force Initialization
Used by the host processor to force initialization of the HDI16 hardware
(which may or may not be necessary, depending on the software design
of the interface). During initialization, the HDI16 transmit and receive
control bits are configured. The type of initialization performed when the
INIT bit is set depends on the state of TREQ and RREQ in the HDI16.
The INIT command, which is local to the HDI16, conveniently configures
the HDI16 into the desired data transfer mode. The effect of the INIT
command is described in Table 25 on page 30. When the host sets the
INIT bit, the HDI16 hardware executes the INIT command. The interface
hardware clears the INIT bit after the command executes.
Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
Freescale Semiconductor
27