EB632 Datasheet, PDF (26/112 Pages) Freescale Semiconductor, Inc – Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M)

HDI16
Table 22 shows the valid HM values and their meaning.
Table 22. HM Host DMA Mode Values (HICR=1)
HM
0
1
0
0
0
1
1
0
1
1
DMA Mode
16-bit words
32-bit words
48-bit words
64-bit words
Mode
Non-DMA Mode
64-bit words. Last read/write (trigger) address: 0x4
48-bit words. Last read/write (trigger) address: 0x5
32-bit words. Last read/write (trigger) address: 0x6
16-bit words. Last read/write (trigger) address: 0x7
9.1.2 2K87M Mask Set ICR Definitions
ICR
2K87M Mask Set Interface Control Register (DMA = 0, HICR = 1)
0x0
Bit
Type
Reset
0
1
HRRA
2
3
HTRA
4
5
6
7
8
9 10 11 12 13 14 15
— HF0 HF1 — INIT
HM
R/W
See Table 24 on page 29
HF2 HF3 HDRQ TREQ RREQ
ICR
2K87M Mask Set Interface Control Register (DMA = 1, HICR = 1)
0x0
Bit
Type
Reset
0
1
HRRA
2
3
HTRA
4
5
6
7
8
9 10 11 12 13 14 15
— HF0 HF1 — INIT
HM
R/W
See Table 24 on page 29
HF2 HF3 — TREQ RREQ
ICR
2K87M Mask Set Interface Control Register (DMA = 0, HICR = 0)
0x0
Bit
Type
Reset
0
1
HRRA
2
3
HTRA
4
5
6
7
8
9 10
— HF0 HF1 — INIT
HDM
R/W
R
See Table 24 on page 29
11 12 13 14 15
HF2 HF3 HDRQ TREQ RREQ
R/W
ICR
2K87M Mask Set Interface Control Register (DMA = 1, HICR = 0)
0x0
Bit 0
1
2
3
4
5
HRRA
HTRA
— HF0
Type
R/W
Reset
Notes: 1. HDM0 when read, TREQ when written
2. HDM0 when read, RREQ when written
6
7
8
9 10
HF1 — INIT
HDM
R
See Table 24 on page 29
11 12
HF2 HF3
R/W
13 14 15
— Note 1 Note 2
R/W
Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2
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