56F8357 Datasheet, PDF (27/177 Pages) List of Unclassifed Manufacturers – 16-BIT HYBRID CONTROLLERS

Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No.
Type
State
During
Reset
Signal Description
GPIOD0
55
(CS2)
GPIOD1
56
(CS3)
P6
Input/
Input, Port D GPIO — These six GPIO pins can be individually
Output
pull-up programmed as input or output pins.
enabled
Output
Chip Select — CS2 - CS7 may be programmed within the EMI
module to act as chip selects for specific areas of the external
L6
memory map.
GPIOD2
57
K6
(CS4)
Depending upon the state of the DRV bit in the EMI Bus
Control Register (BCR), CS2 - CS7 are tri-stated when the
external bus is inactive.
GPIOD3
58
N7
(CS5)
GPIOD4
59
P7
(CS6)
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
At reset, these pins are configured as GPIO.
GPIOD5
60
L7
(CS7)
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOD_PUR register.
TXD0
4
(GPIOE0)
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
B1
Output
In reset, Transmit Data — SCI0 transmit data output
output is
Input/
disabled, Port E GPIO — This GPIO pin can be individually
Output pull-up is programmed as an input or output pin.
enabled
After reset, the default state is SCI output.
RXD0
5
(GPIOE1)
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
D2
Input
Input, Receive Data — SCI0 receive data input
pull-up
Input/
enabled Port E GPIO — This GPIO pin can be individually
Output
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
27
Preliminary