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56F8357 Datasheet, PDF (115/177 Pages) List of Unclassifed Manufacturers – 16-BIT HYBRID CONTROLLERS | |||
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Register Descriptions
6.5.7.7 CLockout Select (CLKOSEL)âBits 4â0
Selects clock to be muxed out on the CLKO pin.
⢠00000 = SYS_CLK (from OCCS - DEFAULT)
⢠00001 = Reserved for factory testâ56800E clock
⢠00010 = Reserved for factory testâXRAM clock
⢠00011 = Reserved for factory testâPFLASH odd clock
⢠00100 = Reserved for factory testâPFLASH even clock
⢠00101 = Reserved for factory testâBFLASH clock
⢠00110 = Reserved for factory testâDFLASH clock
⢠00111 = Oscillator output
⢠01000 = Fout (from OCCS)
⢠01001 = Reserved for factory testâIPB clock
⢠01010 = Reserved for factory testâFeedback (from OCCS, this is path to PLL)
⢠01011 = Reserved for factory testâPrescaler clock (from OCCS)
⢠01100 = Reserved for factory testâPostscaler clock (from OCCS)
⢠01101 = Reserved for factory testâSYS_CLK2 (from OCCS)
⢠01110 = Reserved for factory testâSYS_CLK_DIV2
⢠01111 = Reserved for factory testâSYS_CLK_D
⢠10000 = ADCA clock
⢠10001 = ADCB clock
6.5.8 GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals
for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8157
device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
115
Preliminary
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