MC9S08PA16 Datasheet, PDF (25/33 Pages) Freescale Semiconductor, Inc – MC9S08PA16 Series

Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu Symbol Description
m.
10
t_RI
Rise time input
t_FI
Fall time input
11
t_RO
Rise time output
t_FO
Fall time output
Min.
—
—
Max.
t_Bus - 25
25
Unit
ns
ns
Comment
—
—
SS¹
(OUTPUT)
3
2
10
SPSCK
(CPOL = 0)
5
(OUTPUT)
5
11
4
SPSCK
(CPOL = 1)
(OUTPUT)
10
11
6
7
MISO
(INPUT)
MSB IN²
BIT 6 . . . 1
LSB IN
MOSI
(OUTPUT)
MSB OUT²
8
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA=0)
SS¹
(OUTPUT)
SPSCK
(CPOL = 0)
(OUTPUT)
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
2
3
5
5
6
7
MSB IN²
8
(OUMTPOUSTI)PORT ^{DATA MASTER MSB OUT2}
10
10
BIT 6 . . . 1
9
BIT 6 . . . 1
11
4
11
LSB IN
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA=1)
PORT DATA
MC9S08PA16 Series Data Sheet, Rev. 1, 10/9/2012.
Freescale Semiconductor, Inc.
25