MC13211 Datasheet, PDF (25/70 Pages) Freescale Semiconductor, Inc – ZigBee™- Compliant Platform - 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard plus Microcontroller

5 MCU
5.1 MCU Block Diagram
MCU CORE
BDC
CPU
INTERNAL BUS
DEBUG
MODULE (DBG)
8
PTA7/KBI1P7–
PTA0/KBI1P0
RESET
IRQ
MCU SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
USER FLASH
(61,268 BYTES MAX)
USER RAM
(4096 BYTES MAX)
VDDAD
VSSAD
VREFH
VREFL
VDD
VSS
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ATD1)
INTERNAL CLOCK
GENERATOR (ICG)
LOW-POWER OSCILLATOR
VOLTAGE
REGULATOR
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
IIC MODULE (IIC)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
1-CHANNEL TIMER/PWM
MODULE (TPM1)
4-CHANNEL TIMER/PWM
MODULE (TPM2)
DEDICATED SERIAL
PERIPHERAL INTERFACE
MODULE (SPI)
8
PTB7/AD1P7–
PTB0/AD1P0
PTC7
PTC6
PTC5
PTC4
PTC3/SCL1
PTC2/SDA1
PTC1/RxD2
PTC0/TxD2
PTD7/TPM2CH4
PTD6/TPM2CH3
PTD5/TPM2CH2
PTD4/TPM2CH1
PTD3
PTD2/TPM1CH2
PTD1
PTD0
PTE7
PTE6
PTE5/SPSCK
PTE4/MOSI
PTE3/MISO
PTE2/SS
PTE1/RxD1
PTE0/TxD1
See Note 1.
See Note 1.
Notes
1. All Port F and Port G signals are present on the MCU,
but only the signals used by the MC1321x are designated.
For lowest power operation, all unused I/O should be programmed
as outputs during initialization.
2. Timer channels are limited as noted due to use of Port D I/O for
internal signals.
Figure 15. MCU Block Diagram (HCS08, Version A)
PTG2/EXTAL
PTG1/XTAL
PTG0/BKGD/MS
MC13211/212/213 Technical Data, Rev. 1.5
Freescale Semiconductor
25