34701_07 Datasheet, PDF (23/38 Pages) Freescale Semiconductor, Inc – 1.5 A Switch-Mode Power Supply with Linear Regulator

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
5.0 V
Optional
5.0 V Input
34701
VIN2
VIN1
VBD
VBST
RT
LDRV
CS
LDO
ADDR
SDA
SCL
GND
EN1
EN2
CLKSYN
CLKSEL
FREQ
LFB
RST
BOOT
SW
VOUT
PGND
INV
VDDI
3.3 V
VDDH (I/Os)
VBST
MCU
1.5 V
VDDL (Core)
∆V = 2.1 V
Max. Lead
5.0 V Input Supply
3.3 V I/O Voltage (VLDO)
1.8V Start-Up
1.5 V Core Voltage (VOUT)
∆V = 2.1 V
Max. Lead
∆V = 0.4 V
Max. Lag
∆V = 0.4 V
Max. Lag
Figure 18. Standard Power Up / Down Sequence
in +5.0 V Supply System
STANDARD POWER SEQUENCING
When the power supply IC operates in the Standard Power
Sequencing mode, the switcher output provides the core
voltage for the microprocessor. This situation and operating
conditions are illustrated in Figures 17 and 18. Table 5,
page 17, shows the Power Sequencing mode selection.
INVERTED POWER SEQUENCING
When the power supply IC is operating in the Inverted
Power Sequencing mode, the linear regulator (LDO) output
provides the core voltage for the microprocessor, as
illustrated in Figure 19. Table 5 shows the Power
Sequencing mode selection.
5.0 V
Optional
5.0 V Input
34701
VIN2
VIN1
VBD
VBST
RT
LDRV
CS
LDO
ADDR
SDA
SCL
GND
EN1
EN2
CLKSYN
CLKSEL
FREQ
LFB
RST
BOOT
SW
VOUT
PGND
INV
VDDI
1.5 V
VDDL (Core)
VBST
MCU
3.3 V
VDDH (I/Os)
∆V = 2.1 V
Max. Lead
5.0 V Input Supply
3.3 V I/O Voltage (VOUT)
1.8V Start-Up
1.5 V Core Voltage(VLDO)
∆V = 2.1 V
Max. Lead
∆V = 0.4 V
Max. Lag
∆V = 0.4 V
Max. Lag
Figure 19. Inverted Power Up / Down Sequence in +5.0 V
Supply System
ASSUMED REQUIREMENTS
1. I/O supply voltage not to exceed core voltage by more
than 2.0 V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
Methods of Control
The 34701 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also
achieved through the intrinsic operation of the regulators.
The EN1 and EN2 pins can be used to select the proper
power sequencing mode required by the powered system or
to disable the power sequencing (refer to Table 5).
Intrinsic Operation
For both the LDO and switcher, whenever the output
voltage is below the regulation point, the LDO external Pass
MOSFET is on, or the Buck High-Side MOSFET is on at a
duty cycle controlled by the switcher. Because these devices
are MOSFETs, current can flow in either direction, balancing
the voltages via the common supply pin. The ability to
maintain the MOSFETs on is dependent on the available gate
voltage, and thus the size of the boost regulator storage
capacitor.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34701
23