MC10XS3535 Datasheet, PDF (21/45 Pages) Freescale Semiconductor, Inc – Smart Front Corner Light Switch

FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 10XS3535 is designed for low-voltage automotive and
industrial lighting applications. Its five low R_DS(ON) MOSFETs
(three 10 mΩ and two 35 mΩ) can control the high sides of
five separate resistive loads (bulbs). Programming, control,
and diagnostics are accomplished using a 16-bit SPI
interface.
FUNCTIONAL PIN DESCRIPTION
SUPPLY VOLTAGE (VBAT)
The VBAT pin of the 10XS3535 is the power supply of the
device. In addition to its supply function, this tab contributes
to the thermal behavior of the device by conducting the heat
from the switching MOSFETs to the printed circuit board.
SUPPLY VOLTAGE (VCC)
This is an external voltage input pin used to supply the
digital portion of the circuit and the gate driver of the external
SMART MOSFET.
Ch.1
Ch.2
Ch.3
Ch.4
Total
0° 90° 180° 270° 0°
GROUND (GND)
This pin is the ground of the device.
CLOCK INPUT / WAKE-UP OUTPUT (CLOCK)
When the part is in Normal Mode (RST=1), the PWM
frequency and timing are generated from the rising edge of
clock input by the PWM module. The clock input frequency is
the selectable factor 2⁷ = 128 or 2⁸ = 256 of the PWM
frequency per output, depending PR bit value.
The OUT1:6 can be controlled in the range of 4% to 96%
with a resolution of 7 bits of duty cycle (bits D[6:0]).
The following table describes the PWM resolution.
On/Off Duty cycle (7 bits
(Bit D7)
resolution)
Output state
0
X
OFF
1
0000000
PWM (1/128 duty cycle)
1
0000001
PWM (2/128 duty cycle)
1
0000010
PWM (3/128 duty cycle)
1
1111111
fully ON
The timing includes four programmable PWM switching
phases (0°, 90°, 180°, and 270°) to improve overall EMC
behavior of the light module.
The amplitude of the input current is divided by four while
the frequency is 4 times the original one. The two following
pictures illustrate this behavior.
Ch.1
Ch.2
Ch.3
Ch.4
Total
0° 90° 180° 270° 0°
The synchronization of the switching phases between
different IC is provided by an SPI command in combination
with the CS input. The bit in the SPI is called PWM sync
(initialization register).
In Normal mode, no PWM feature (100% duty cycle) is
provided in the following instances:
•with the following SPI configuration: D7:D0=FF.
•In case of clock input signal failure (out of f _PWM), the
outputs state depends of D7 bit value (D7=1=ON) in
Normal mode.
In Fail mode, the ouputs state depend on IGN, FLASHER,
and FOG pins.
If RST=0, this pin reports the wake-up event for wake=1
when VBAT and VCC are in operational voltage range.
LIMP HOME INPUT (LIMP)
The Fail mode of the component can be activated by this
digital input port. The signal is “high active”, meaning the Fail
mode can be activated by a logic high signal at the input.
Analog Integrated Circuit Device Data
Freescale Semiconductor
10XS3535
21