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MC9S08DZ60ACLH Datasheet, PDF (209/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features | |||
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
Table 11-8. IICC2 Field Descriptions
Field
Description
7
GCAEN
6
ADEXT
2â0
AD[10:8]
General Call Address Enable. The GCAEN bit enables or disables general call address.
0 General call address is disabled
1 General call address is enabled
Address Extension. The ADEXT bit controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
Slave Address. The AD[10:8] ï¬eld contains the upper three bits of the slave address in the 10-bit address
scheme. This ï¬eld is only valid when the ADEXT bit is set.
11.4 Functional Description
This section provides a complete functional description of the IIC module.
11.4.1 IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
⢠Start signal
⢠Slave address transmission
⢠Data transfer
⢠Stop signal
The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication
is described brieï¬y in the following sections and illustrated in Figure 11-9.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
209
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