33883 Datasheet, PDF (16/21 Pages) Freescale Semiconductor, Inc – H-Bridge Gate Driver IC

FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
GATE PROTECTION
The low-side driver is supplied from the built-in low-drop
regulator. The high-side driver is supplied from the internal
charge pump buffered at CP_OUT.
The low-side gate is protected by the internal linear
regulator, which ensures that V_{GATE_LS} does not exceed the
maximum V_GS. Especially when working with the charge
pump, the voltage at CP_OUT can be up to 65 V. The high-
side gate is clamped internally in order to avoid a V_GS
exceeding 18 V.
Gate protection does not include a fly-back voltage clamp
that protects the driver and the external MOSFET from a fly-
back voltage that can occur when driving inductive load. This
fly-back voltage can reach high negative voltage values and
needs to be clamped externally, as shown in Figure 12.
LR_OUT CP_OUT
IN _Output ^OUT
Driver
M₁
GATE_HS
SRC_HS
D_{c l}
L₁
IN _Output ^OUT
Driver
M₂
GATE_LS
V_CC
V_GS < 14 V
Under All
Conditions
Inductive
Flyback Voltage
Clamp
Figure 12. Gate Protection and Flyback Voltage Clamp
LOAD DUMP AND REVERSE BATTERY
V_CC and V_CC2 can sustain load a dump pulse of 40 V and
double battery of 24 V. Protection against reverse polarity is
ensured by the external power MOSFET with the free-
wheeling diodes forming a conducting pass from ground to
V_CC. Additional protection is not provided within the circuit.
To protect the circuit an external diode can be put on the
battery line. It is not recommended putting the diode on the
ground line.
TEMPERATURE PROTECTION
There is temperature shutdown protection per each half-
bridge. Temperature shutdown protects the circuitry against
temperature damage by switching off the output drivers. Its
typical value is 175°C with an hysteresis of 15°C.
DV/DT AT V_CC
V_CC voltage must be higher than (SRC_HS voltage minus
a diode drop voltage) to avoid perturbation of the high-side
driver.
In some applications a large dV / dt at terminal C2 owing to
sudden changes at V_CC can cause large peak currents
flowing through terminal C1, as shown in Figure 13.
For positive transitions at terminal C2, the absolute value
of the minimum peak current, I _C1min, is specified at 2.0 A for
a t _C1min duration of 600 ns.
For negative transitions at terminal C2, the maximum peak
current, I_C1max, is specified at 2.0 A for a t _C1max duration of
600 ns. Current sourced by terminal C1 during a large dV / dt
will result in a negative voltage at terminal C1 (Figure 13).
The minimum peak voltage V_C1min is specified at -1.5 V for a
duration of t _C1max = 600 ns. A series resistor with the charge
pump capacitor (Ccp) capacitor can be added in order to limit
the surge current.
33883
16
Analog Integrated Circuit Device Data
Freescale Semiconductor