908E625 Datasheet, PDF (15/48 Pages) Freescale Semiconductor, Inc – Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication

FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 908E625 device was designed and developed as a
highly integrated and cost-effective solution for automotive
and industrial applications. For automotive body electronics,
the 908E625 is well suited to perform complete mirror, door
lock, and light-levelling control all via a three-wire LIN bus.
This device combines an standard HC08 MCU core
(68HC908EY16) with flash memory together with a
SMARTMOS™ IC chip. The SMARTMOS™ IC chip
combines power and control in one chip. Power switches are
provided on the SMARTMOS™ IC configured as half-bridge
outputs with one high-side switch. Other ports are also
provided; they include Hall-effect sensor input ports, analog
input ports, and a selectable HVDD terminal. An internal
voltage regulator is provided on the SMARTMOS™ IC chip,
which provides power to the MCU chip.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables the device to
be compatible with three-wire bus systems, where one wire is
used for communication, one for battery, and the third for
ground.
FUNCTIONAL TERMINAL DESCRIPTION
See Figure 1 for a graphic representation of the various
terminals referred to in the following paragraphs. Also, see
the terminal diagram on Figure 3 for a depiction of the
terminal locations on the package.
PORT A I/O TERMINALS (PTA0:4)
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. PTA0:PTA4 are shared with the keyboard interrupt
terminals, KBD0:KBD4.
The PTA5/SPSCK terminal is not accessible in this device
and is internally connected to the SPI clock terminal of the
analog die. The PTA6/SS terminal is likewise not accessible.
For details refer to the 68HC908EY16 datasheet.
PORT B I/O TERMINALS (PTB1, PTB3:7)
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. All terminals are shared with the ADC module. The
PTB6:PTB7 terminals are also shared with the Timer B
module.
PTB0/AD0 is internally connected to the ADOUT terminal
of the analog die, allowing diagnostic measurements to be
calculated; e.g., current recopy, V_SUP, etc. The PTB2/AD2
terminal is not accessible in this device.
For details refer to the 68HC908EY16 datasheet.
PORT C I/O TERMINALS (PTC2:4)
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. For example, PTC2:PTC4 are shared with the ICG
module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI
SPI terminals of the analog die.
For details refer to the 68HC908EY16 datasheet.
PORT D I/O TERMINALS (PTD0:1)
PTD1/TACH1 and PTD0/TACH0/BEMF are special-
function, bidirectional I/O port terminals that can also be
programmed to be timer terminals.
In step motor applications the PTD0 terminal should be
connected to the BEMF output of the analog die in order to
evaluate the BEMF signal with a special BEMF module of the
MCU.
PTD1 terminal is recommended for use as an output
terminal for generating the FGEN signal (PWM signal) if
required by the application.
PORT E I/O TERMINAL (PTE1)
PTE1/RXD and PTE0/TXD are special-function,
bidirectional I/O port terminals that can also be programmed
to be enhanced serial communication.
PTE0/TXD is internally connected to the TXD terminal of
the analog die. The connection for the receiver must be done
externally.
EXTERNAL INTERRUPT TERMINAL (IRQ)
The IRQ terminal is an asynchronous external interrupt
terminal. This terminal contains an internal pull-up resistor
that is always activated, even when the IRQ terminal is pulled
LOW.
For details refer to the 68HC908EY16 datasheet.
EXTERNAL RESET TERMINAL (RST)
A Logic [0] on the RST terminal forces the MCU to a known
startup state. RST is bidirectional, allowing a reset of the
entire system. It is driven LOW when any internal reset
source is asserted.
This terminal contains an internal pull-up resistor that is
always activated, even when the reset terminal is pulled
LOW.
For details refer to the 68HC908EY16 datasheet.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E625
15