33784 Datasheet, PDF (15/30 Pages) Freescale Semiconductor, Inc – DSI 2.02 Sensor Interface

10MHz Clock
Received Message
From MASTER
Data
Bus Controller _{Data Clock}
Command Buffer
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
CRC ^Latch
Check
DBUS Registers
INIT
REQ STATUS
REQ AN0
I/O CONTROL
REQ ID
REQ AN1
CLEAR
FORMAT CONTROL
TEST
Load Enable
Data Clock
10MHz Clock
Response Shifter
CRC Generator
DATA OUT [2:0]
I/O [2:0]
AD_SEL
AD_DATA [9:0]
TEST
I_Response ON
SEL
Figure 6. DBUS Slave Logic Block Diagram
COMMUNICATION FORMAT
DBUS messages are composed of individual words
separated by a frame delay. Transfers are full duplex.
Command messages from the master occur at the same time
as responses from the slaves. Slave responses to commands
occur during the next command message. This allows slaves
time to decode the command, retrieve the information, and
prepare to send it to the master. A bus traffic example is
shown in Figure 7.
The example shows three commands separated by the
minimum frame delay followed by a command after a longer
delay.
Figure 7. Bus Traffic Example
Analog Integrated Circuit Device Data
Freescale Semiconductor
33784
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