MC9S12E128V1 Datasheet, PDF (148/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.5 Port S
Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0
and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 >
general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the
SPI block description chapter for information on enabling and disabling the SPI.
When the SCI1 receiver and transmitter are enabled, the PS[3:2] pins become TXD1 and RXD1
respectively. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and
RXD0 respectively. Refer to the SCI block description chapter for information on enabling and disabling
the SCI receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
3.3.5.1 Port S I/O Register (PTS)
7
R
PTS7
W
SPI:
SS
6
PTS6
SCK
5
PTS5
MOSI
4
PTS4
MISO
3
PTS3
2
PTS2
1
PTS1
0
PTS0
SCI1/SCI0
:
Reset
0
TXD1
RXD1
0
0
0
0
0
Figure 3-29. Port S I/O Register (PTS)
TXD0
0
RXD0
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
3.3.5.2 Port S Input Register (PTIS)
7
R PTIS7
W
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 3-30. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIS1
u
0
PTIS0
u
MC9S12E128 Data Sheet, Rev. 1.07
148
Freescale Semiconductor